1. Field of the Invention
The present invention relates to a method for designing an integrated circuit device.
2. Description of the Related Art
In recent years, technologies for integrating various circuit elements such as transistors and inverters into large scale integrated circuit (LSI) devices have been developed and such integrated circuit devices have been widely commercialized. However, in the integrated circuit devices, the performance degradation due to hot carriers will not be negligible.
For example, inverts normally play a major role in an integrated circuit device. In an inverter, during a transition time period from the timing when an input signal rises to the timing when an output signal falls, hot carriers are generated to degrade the performance and deteriorate the output characteristics. If such degradation with time in the performance of circuit elements due to hot carriers goes beyond an allowable limit during the guaranteed period of the integrated circuit device, the integrated circuit device will be tagged as defective. This will be explained later in detail.
In a first prior art method, in order to avoid such a situation, integrated circuit devices are so designed as to make them perform without degrading beyond the allowable limit, at least during the guaranteed period of the device. More specifically, in the course of designing an integrated circuit device by arranging various circuit elements, the degradation with time of each of the circuit elements is simulated using a simulation method such as "SPICE" and various design data. Thus, the performance of each of the circuit elements of the integrated circuit device at the end of the guaranteed period can be anticipated by the simulation method. If the anticipated performance is not found within an allowable range, the design and layout of the integrated circuit device will have to be changed.
On the other hand, while hot carriers are generated in a circuit element such as an inverter during its signal transition period, it will be subject to degradation due to hot carriers and other factors less if the transition period is shorter. Since the signal transition time of the circuit element depends on its load capacity, a circuit element having a small load capacity shows little degradation of performance attributable to hot carriers. The load capacity is the capacity of an output line of the circuit element, and hence depends on the length of the output line and the downstream circuit elements connected to it.
In a second prior art method (see: JP-A-3-142964), after an integrated circuit device is designed, the load capacity of each of the circuit elements of the integrated circuit device is calculated and is then divided by the rising time and the transfer factor of the circuit elements. The calculated value is then compared with a reference value and, if the former exceeds the latter, the design of the circuit element will be modified.
In the above-described prior art methods, it is possible to design an integrated circuit device such that its performance will not degrade beyond an allowable limit during the guaranteed period of the device by taking the degradation with time of each of the circuit elements due to hot carriers into consideration.
In the first prior art method, the use of a simulation method such as "SPICE" for an integrated circuit device normally comes into the scene after the completion of the entire design of the integrated circuit device to validate the reliability of the circuit elements. In other words, if any of the circuit elements is found defective as a result of the simulation, the finished integrated circuit device has to be modified. Similarly, the second prior art method also checks the reliability of each of the circuit elements of an integrated circuit device after the completion of the entire design of the device and then corrects or modifies the design and layout of the device if necessary.
However, it is not easy to modify the finished integrated circuit device because, if one of the circuit elements is modified, the performance of the remaining circuit elements can be affected by the modification and, therefore, the performance of the modified integrated circuit device will have to be simulated once again. Particularly, for an integrated circuit device that is normally constructed by a large number of circuit elements as integral parts thereof, if such simulations and modifications are repeated for a number of times on each of the circuit elements, the time consumed for the design of the integrated circuit device will be enormous when the design is completed.